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Facebook Digital Design Engineer, SOC in Redmond, Washington


Facebook Reality Labs, or FRL, focuses on delivering Facebook's vision through Augmented Reality (AR). Compute power requirements of Augmented Reality require custom silicon. Facebook Silicon team is driving the state of the art forward with breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable AR devices where our real and virtual world will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistor, through architecture, to firmware, and algorithms.

We are growing our Digital Design Engineering team within AR Silicon and are seeking engineers at all levels who will work with a world-class group of researchers and engineers using your digital design skills to implement and contribute to development and optimization of state of the art SoCs as well as vision/sensing algorithms. You will also support the Silicon Architects in developing and implementing the next generation custom and semi-custom mixed signal ICs to drive our industry leading virtual and augmented reality systems.

This role can be based in Redmond, WA or Menlo Park, CA.

Required Skills:

  1. Contribute to the development of efficient µArchitectures and contribute to ASIC digital µArchitecture, design and verification

  2. Understand our in-house IPs needed and how they need to be integrated, connected and verified

  3. Drive the top-level µArchitecture definition and develop the necessary RTL

  4. Drive the chip-level integration, verification plan development and verification

  5. Supervise the RTL-to-GDS flow and assist with synthesis and timing closure

  6. Support the test program development, chip validation and chip life until production maturity

  7. Work with FPGA engineers to perform early prototyping

  8. Support hand-off and integration of blocks into larger SOC environments

  9. Assist with Algorithm analysis, verification and improvement

  10. Contribute to ASIC digital architecture, design and verification

  11. Ability to communicate clearly

Minimum Qualifications:

  1. 4+ years of experience as a Digital Design Engineer and/or a Chip Lead

  2. Experience in RTL coding, synthesis and/or SoC Integration

  3. Experience in digital design µArchitecture

  4. BS Electrical Engineering/Computer Science or equivalent experience

Preferred Qualifications:

  1. System Verilog OVM/UVM experience

  2. Python (or similar) scripting experience

  3. Experience in SoC integration and ASIC architecture

  4. Experience in DFT/Testability requirement and test program definition

  5. Experience using High Speed interfaces like PCIe, USB, MIPI

  6. Master’s degree in EE

Industry: Internet

Equal Opportunity: Facebook is proud to be an Equal Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Facebook is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@fb.com.