Facebook ASIC Engineer, Physical Design in Sunnyvale, California
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Facebook is hiring ASIC Physical Design Engineers within our Infrastructure organization. We are looking for individuals with experience in backend implementation from Netlist to GDSII in low power and high-performance designs to build efficient System on Chip (SoC) and IP for data center applications.
Develop and own physical design implementation of multi-hierarchy low-power and high-performance designs, including physical-aware logic synthesis, floorplan, place and route, clock tree synthesis, static timing analysis, IR drop, EM, and physical verification in advanced technology nodes.
Resolve design and flow issues related to the physical design, identify potential solutions, and drive execution.
Deliver physical design of an end-to-end IP or integration of ASIC/SoC design and point out lower power and higher performance trade-offs.
Define and implement schemes, including semi-custom placement and routing, to improve performance and power.
Work with the RTL design team to understand partition architecture and drive physical aspects early in the design cycle.
Interface with the RTL design team to drive design modifications to resolve congestion/timing issues and implement functional ECO’s.
Use EDA tool-based programming and scripting techniques to automate and improve throughput and quality.
Interact with tool vendors to drive tool fixes and flow improvements. Perform tool evaluations of new vendor tools and functions.
B.S. or M.S. degree in Electrical Engineering or equivalent similar experience.
10+ years experience in physical design and timing closure.
Knowledge of RTL2GDSII flow and design tapeouts in 7nm or below process technologies.
Experience with EDA tools like DC/Genus, Innovus/ICC2, Primetime, Redhawk/Voltus, or Calibre.
Hands-on experience in floor planning, place & route, power and clock distribution, and timing convergence of high-frequency designs.
Knowledge of geometry/process/device technology implications on physical design.
Experience with large SOC designs (>20M gates) with frequencies over 1GHZ.
Interpersonal, teamwork, and communication skills and experience interfacing with cross-functional teams, IP, and EDA vendors.
Programming/scripting skills: TCL, Python, Perl or Shell.
Experience in full chip floor planning, partitioning, budgeting, and power grid planning.
Experience with low power implementation, power gating, multiple voltage rails, UPF/CPF knowledge.
Experience in planning, implementing, and analyzing high-speed clock distribution networks. Experience with alternate strategies for clock distribution, including standard trees, mesh, H-Tree, and clock power reduction techniques.
Knowledge of static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions.
Knowledge of Circuit design, device physics, and deep sub-micron technology.
Experience in the physical design of data-path intensive designs.
Equal Opportunity: Facebook is proud to be an Equal Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Facebook is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at email@example.com.