Job Information
Meta Display Driver IC Engineer (Pixel Pipeline) in Sunnyvale, California
Summary:
Meta Reality Lab is the world leader in the design of virtual and augmented reality systems. Come work alongside expert engineers and research scientists to create the technology that makes VR pervasive and universal. Join the adventure of a lifetime as we make science fiction real and change the world. The Display Architecture Team within the VR organization is seeking a Display Driver IC Engineer to lead the implementation of Meta’s proprietary display IP for VR displays. As a member of the VR Display Team, the successful candidate will be working closely with Display Driver IC (DDIC) architects, Visual Quality team, and DDIC vendors to design, evaluate performance, and embed Meta’s proprietary visual quality IP within the vendor's DDIC for future VR products. This role offers involvement in a mix of forward-looking and product-critical projects, and requires close collaboration with multiple teams within the Meta Reality Labs.
Required Skills:
Display Driver IC Engineer (Pixel Pipeline) Responsibilities:
Define hardware architecture of proprietary display IP for VR displays in collaboration with display algorithm architects.
Design and implement the algorithm in Verilog with optimized gate-count, meeting performance targets.
Collaborate with DDIC vendors to ensure consistency between IP architecture and the DDIC design.
Collaborate with vendors to embed IP within the vendor’s DDIC. Supervise chip-level verification.
Participate in DDIC design reviews with vendors and assess overall digital design flow including verification coverage, clock synthesis, timing signoff.
Collaborate with the system team to bring up and test the algorithm for production readiness.
Minimum Qualifications:
Minimum Qualifications:
Masters Degree in Electrical Engineering, Computer Science, or equivalent work experience.
10+ years of industry work experience in the field of IC design and development.
Understanding of the front-end digital design flow: RTL design, logic synthesis, timing verification.
Understanding of pixel pipeline for Displays and DDIC architecture.
Experience with at least one programming language such as Matlab, Python or C++.
Effective communication skills.
Preferred Qualifications:
Preferred Qualifications:
Ph.D. in Electrical Engineering.
Hands-on experience with FPGA prototyping for display applications.
Experience with architecture and design of display IP such as sub-pixel rendering, foveation, Mura, burn-in compensation algorithms.
Familiar with compression IP design such as DSC.
Public Compensation:
$170,000/year to $240,000/year + bonus + equity + benefits
Industry: Internet
Equal Opportunity:
Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.
Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@fb.com.